Lauri
Koskinen
Docent, Department of Computing
Professor of Practice
Integrated circuits
Links
Areas of expertise
System-on-Chip architecture: Low-power processing
Verification and sign off
Neuromorphic computing / CiM
On-chip security
Mixed-Mode Processing
Audio & Video analysis
Ultra-low-power digital design: Processor architecture / RISC-V
Ultra-low-power digital design: Processor architecture / RISC-V
Sub- and near-threshold design
Library characterization
Semiconductor statistics
R&D Commercialization / IP protection
Semiconductor business development: Patenting
Semiconductor statistics
R&D Commercialization / IP protection
Semiconductor business development: Patenting
Marketing
Power management: Integrated DC-DC converters
Power management: Integrated DC-DC converters
LDOs
Project management / team lead
Project management / team lead
Biography
Wide expertise ranging from ultra-low-power aspects of deep submicron transistors to the high-level realization of various systems (microcontrollers, deep learning, wireless biomedical sensors, audio and video coders).
Proven track record in commercializing R&D
Excellent communication skills.
Wide range of research contacts from IC design to medical expertise.
Considerable skills in innovative project proposal drafting
Teaching
Processor architecture, Digital and mixed-mode IC design, modern EDA design flow
Research
Energy Minimization in small to big systems using both conventional and unconventional methods.
Publications
A robust ultra-low voltage CPU utilizing timing-error prevention (2015)
Journal of Low Power Electronics and Applications
(Vertaisarvioitu alkuperäisartikkeli tai data-artikkeli tieteellisessä aikakauslehdessä (A1))
Power Optimizations for Transport Triggered SIMD Processors (2015)
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))
A Fully Integrated Self-Oscillating Switched-Capacitor DC-DC Converter for Near-Threshold Loads (2015)
IEEE Asian Solid-State Circuits Conference (A-SSCC)
(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))
Recursive Algorithms in Memristive Logic Arrays (2015)
IEEE Journal of Emerging and Selected Topics in Circuits and Systems
(Vertaisarvioitu alkuperäisartikkeli tai data-artikkeli tieteellisessä aikakauslehdessä (A1))
Fully Integrated DC-DC Converter and a 0.4V 32-bit CPU with Timing-Error Prevention Supplied from a Prototype 1.55V Li-ion Battery (2015)
Symposium on VLSI Circuits-Digest of Papers
(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))
K-means clustering in a memristive logic array (2015)
IEEE NANO 2015 15th INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY
(Vertaisarvioimaton konferenssijulkaisu (B3))
Ultra-Wide Voltage Range 32-bit RISC CPU with Timing-Error Prevention in 28nm CMOS (2014)
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))
A cellular computing architecture for parallel memristive stateful logic (2014)
Microelectronics Journal
(Vertaisarvioitu alkuperäisartikkeli tai data-artikkeli tieteellisessä aikakauslehdessä (A1))
Effects of Back-Gate Bias on Switched-Capacitor DC-DC Converters in UTBB FD-SOI (2014)
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))
A cellular architecture for memristive stateful logic (2014)
International Workshop on Cellular Nanoscale Networks and their Applications, International Workshop on Cellular Nanoscale Networks and their Applications
(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))